As a circuit which samples an analog signal and holds an analog value, an S/H (Sample & Hold or also referred to as sample hold) circuit is known. This S/H circuit may also be called as a track hold circuit (hereinafter, this circuit will be referred to as a track hold circuit).
Like most of electronic circuits, data conversion circuits such as A/D conversion circuits or D/A conversion circuit using the track hold circuits are required to exhibit a still higher processing speed.
There are some techniques being proposed for satisfying such demands.
For example, there is a technique which uses a time interleave system that converts data by placing a plurality of data conversion circuits in parallel (Patent Document 1).
The time interleave system is a system which sequentially switches and operates a plurality of same circuits in order to increase the operation clock frequency equivalently.
Through placing two or more track hold circuits in parallel and operating each of the track hold circuits in a time interleave manner, the conversion speed can be doubled or more.
FIG. 6 is a block diagram showing an example of the structure of a track hold circuit that uses the time interleave system of such related technique.
In an electronic circuit system 201 of FIGS. 6, 11 and 18-25 are track hold circuits, Sin is an analog input signal terminal, and CLK1 and CLK8-CLK15 are clock signal input terminals.
An analog signal is inputted to the analog signal input terminal Sin of the track hold circuit 11. Each of eight outputs of the track hold circuit 11 is connected to the track hold circuits 18-25. Further, respective clock signals are inputted to the clock input terminals CLK1 and CLK8-CLK15 of the track hold circuits 11 and 18-25, and each of the track hold circuits 11 and 18-25 operates based thereupon.
In the electronic circuit system 210, a first hierarchy K1 (an input stage, a first stage) is formed by the track hold circuit 11. Further, in the electronic circuit system 210, a second hierarchy K2 (a final output stage, a second stage) is formed by the track hold circuits 18-25.
Now, the operation of the related technique shown in FIG. 6 will be described by referring to FIG. 7.
FIG. 7 is a timing chart showing timings of clock signals inputted to the clock signal input terminals CLK1 and CLK8-CLK15, and (A)-(I) of FIG. 7 show waveforms of each of those clock signals.
For example, the track hold circuit 11 operates at 16 GHz and track-holds the analog signal inputted from the analog input signal Sin.
The track hold circuits 18-25 of the second stage group track-hold the analog signals at 2 GHz while shifting the phases thereof form each other.
An analog signal is tracked at the timing of T001 in FIG. 7, and it is held at the timing of T002 in FIG. 7.
In the meantime, the track hold circuit 18 tracks an output signal of the track hold circuit 11 at T003 in FIG. 7, and holds it at the timing of T004.
Similarly, the track hold circuits 19-25 operate while shifting the phases thereof by 45 degrees (=360 degrees divided by 8 phases) from each other to track-hold the output signal of the track hold circuit 11.
That is, the track hold circuits 18-25 operate at 2 GHz but the phases thereof are shifted from each other by one period of 16 GHz, so that one of the track hold circuits 18-25 has tracked and held the clock signal at the point where one clock signal of 16 GHz of the track hold circuit 11 passes. Thus, the related technique shown in FIG. 6 is substantially equivalent to operating at 16 GHz.
As a result, through placing eight track hold circuits of 2 GHz in parallel and time-interleave operating each of those track hold circuits, it is possible to constitute the track hold circuit operating at 16 GHz.    Patent Document 1: Japanese Unexamined Patent Publication Hei 9-252251    Patent Document 2: Japanese Unexamined Patent Publication Hei 8-079080